The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors, or other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes. Furthermore, advanced processes are being used which are much more tolerant to minute inaccuracies during processing. However, these processes often make extraordinary demands upon the chemistry of the etching process. Oxide etching has presented some of the most difficult demands. Oxide etching refers to the etching of layers of silicon dioxide, silica glass such as BPSG, and related oxide materials that serve as electrical insulators. Advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective oxide layers. Small contact or via holes need to be etched through each of the oxide layers.
An example of an advanced oxide etching process is a self-aligned contact (SAC) process. An example of a SAC structure for two MOS transistors is illustrated in the cross-sectional view of FIG. 1. Two polysilicon lines 10, 12 are deposited and defined over a silicon substrate 14. Each polysilicon line 10, 12 forms a gate structure intended to operate as a gate electrode for a respective MOS transistor. The polysilicon lines 10, 12 act as a mask for the ion implantation of a p-type or n-type dopant into a source region 16 for both of the MOS transistors. Unillustrated drain regions are also formed to complete the principal portions of the MOS transistors. An LPCVD process is used to coat a thin conformal layer 18 of silicon nitride (Si.sub.3 N.sub.4) on the exposed silicon substrate 14 and on the polysilicon lines 10, 12. A narrow portion 20 of the silicon nitride layer 18 is formed over the silicon substrate 14 in a gap 22 between the nitride-covered gate structures 10, 12. This narrow portion 20 is removed by a post nitride etch following the oxide etch to expose the underlying silicon 14 for contacting. The gap 22 is made as small as possible consistent with subsequent processing in order to increase the integration level.
An oxide layer 24 is then deposited, usually by plasma-enhanced chemical vapor deposition (PECVD), to act as an interlevel dielectric. Considerations of dielectric breakdown with normal operating voltages limit the minimum thickness of the oxide layer 24 to between 0.5 .mu.m and 1 .mu.m. A photolithographic step including depositing and photographically defining a photoresist mask 25 followed by an oxide etch forms a contact hole 26 extending to the narrow silicon nitride portion 20 above the silicon source region 16. Following the post nitride etch to remove the narrow silicon nitride portion 20, the contact hole 26 is filled with aluminum or other conductor to form a plug electrically connecting the source region 16 of the two MOS transistors to the wiring level above the dielectric layer 24. The silicon nitride layer 18 acts as an electrical insulator relative to the aluminum plug to isolate the plug from the polysilicon lines 10, 12.
The SAC oxide etch process must satisfy several difficult requirements. The contact hole 26 should be as narrow as possible to increase the integration level, but the oxide thickness is relatively fixed at a significantly larger length. As a result, the contact hole 26 has a high aspect ratio of depth to width. A high aspect ratio can be accomplished only with a highly anisotropic etch, with the wall slope being greater than, for example, 85.degree. and preferably close to 90.degree..
In view of the large number of structures on a wafer and the variations in oxide thickness, it is highly desirable that the oxide etch be highly selective to silicon nitride, that is, that the etch process etch oxide 24 much more quickly than the underlying silicon nitride 18. The contact hole 26 can then be over etched, for example by 100% of the design depth, to accommodate non-uniformities or process variations, thus assuring that the contact hole reaches the bottom nitride portion 20 over the silicon source region 16. But if the etching manifests high selectivity, there is little etching of the silicon nitride so the source region 16 can be made relatively thin.
If the gap 22 is made very small, various considerations may limit the width of the contact hole 26 to be greater than the size of the gap 22. Also, there may be some uncontrolled variations in the position of the contact hole 26. With a nitride selective etch, the contact hole 26 can overlap the polysilicon lines 10, 12, and small variations of the location of the contact hole 26 can be accommodated while contact to the silicon is still assured. A SAC etch is usually also selective to silicon.
As illustrated, the width of the contact hole 26 is about the same as that of the gap 22 between the nitride-covered polysilicon lines 10, 12, but the photolithographic variations cause the contact hole 26 to be offset from the gap 22 and to expose a corner 27 of the nitride layer. Alternatively, the width of the contact hole 26 may be made significantly larger than the width of the gap 22 so that two nitride corners 27 are exposed. Since the nitride corners 27 are exposed the longest to the oxide etch and the acute corner geometry favors etching, nitride corner loss is often the most critical selectivity issue in contact or via etching. The etch process is subject to other constraints, such as the selectivity to the photoresist 25, which is prone to form facets 28. If the facets 28 extend to the underlying oxide 24, the resolution of the photolithography is degraded. However, nitride comer loss is generally considered to be the most demanding selectivity requirement in a SAC process.
Another difficult oxide etch technique not necessarily involving nitrides is a bi-level contact. A single etch is used to simultaneously etch through an upper oxide inter-level layer to a thin polysilicon line underlying the upper oxide layer and also etch through both the upper and a lower oxide inter-level layer to another polysilicon line underlying the lower oxide layer. This technique requires very high selectivity to silicon to avoid etching through the upper polysilicon line while the lower oxide layer is being etched through.
It is now known that reasonably good oxide etch processes can be achieved by using a fluorocarbon or hydrofluorocarbon etching gas, such as the respective types CF.sub.4 or CHF.sub.3 or higher-order compounds of the two types. These two types of etchants may be referred to as a hydrogen-free fluorocarbon and a hydrofluorocarbon although the common terminology includes both hydrogen-free fluorocarbons and hydrofluorocarbons as fluorocarbons. Fluorocarbons formed in linear chains are referred to as fluoroalkanes, using standard organic chemistry nomenclature. Under the proper conditions, the fluorocarbon forms a low-fluorine polymer on the silicon and the nitride but not on the oxide. Thereby, the oxide is etched but the silicon and nitride are not. However, if the fluorine content of the etching gas is too high, the fluorine can etch the underlying silicon or nitride and the selectivity is lost. It is believed that CF.sub.x radicals selectively etch oxide over silicon or nitride, but F radicals etch silicon and nitride as well.
The polymer introduces a further problem of etch stop. In narrow deep holes being etched, that is, holes of high aspect ratio, excess polymer is formed over the oxide walls and floor, and etching may stop at a point before the nitride floor is reached. After etch stop, further exposure to the etching plasma does not deepen the hole. Etch stop can also occur in narrow, deep trenches. The critical dimension for a trench is its width, while for a circular hole it is its diameter. Etch stop depends not only upon the aspect ratio of the hole but also upon its critical dimension. As the critical dimension is being pushed to below 0.5 .mu.m and as aspect ratios are being pushed well above two, etch stop has become a serious problem.
Thus, it is seen that advanced oxide etching must satisfy numerous difficult requirements. Further, in commercial applications, the oxide etch rate must be moderately high for reasons of economy in the use of expensive equipment and clean-room floor space. Several approaches have been suggested for addressing these problems. The success of these approaches must be evaluated in terms of a yet further problem of uniformity or reproducibility. Often a process can be finely optimized to satisfy the various requirements of selectivity, etch rate, etc. However, the optimized etching parameters may produce the required results only for a narrow range of the parameters; that is, the process window is narrow. A narrow process window may mean that random fluctuations or uncontrollable drift may bring the process out of specification from one wafer to another, and especially from day to day. Examples of such variations are reaching thermal steady state after the start of a run or after shut down for maintenance, aging of a chamber part, and replacement of a seasoned chamber part with a new part.
Also, in view of the large number of steps involved in advanced circuitry, etching rates need to be uniform to a few percent over the wafer. If the process window is too narrow, the conditions at the center of the wafer may differ sufficiently from those at the wafer edge to produce significantly different results. Hence, a wide process window is required for a commercially feasible process.
In the past, the most typical etchant gases have been CF.sub.4 and CHF.sub.3. The hydrofluorocarbon CHF.sub.3 has been generally assigned a role of promoting polymerization. Higher-order fluorocarbons have been suggested, and some have been used commercially. Yanagida in U.S. Pat. No. 5,338,399 suggests the use of cyclic fluorocarbons, especially saturated hydrogen-free fluorocarbons such as c-C.sub.3 F.sub.6 and c-C.sub.4 F.sub.8 which have a monomeric composition of --CF.sub.2 --, that is, a C/F ratio of 1/2. Yanagida's results were obtained in a magnetically enhanced capacitively coupled reactor operating at a relatively high pressure of 266 milliTorr, and he observed enhanced selectivity at low temperatures. Yanagida has also disclosed the use of hexafluoropropylene in Japanese Laid-Open Patent Applications 61-133630, 3-276626, and 4-346428.
Tahara et al. in U.S. Pat. No. 5,356,515 suggest the additional use of carbon monoxide (CO) in a similar reactor in combination with CF.sub.4 or CHF.sub.3 in order to achieve high selectivity. They ascribe the effectiveness of CO to its reducing the CF.sub.2 radicals which would otherwise form a polymer on the SiO.sub.2 walls of the hole being etched.
Arleo et al. in U.S. Pat. No. 5,176,790 disclose a low-density plasma process for etching vias through an oxide layer to an underlying metal layer. Among several embodiments is a process utilizing high-order linear fluorocarbons and hydrofluorocarbons C.sub.x H.sub.y F.sub.z, wherein x is 3 to 6, y is 0 to 3, and z is 2x-y+2. He suggests some examples including C.sub.3 F.sub.8, C.sub.3 HF.sub.7, C.sub.3 H.sub.2 F.sub.6, and C.sub.3 H.sub.3 F.sub.5. Arleo et al. favor pressures in the range of 10 to 20 milliTorr although a wider pressure range is suggested.
Marks et al. in U.S. patent application, Ser. No. 07/826,310, filed Jan. 24, 1992 disclose a plasma process for etching contact holes through an oxide layer to an underlying silicon layer. One of the embodiments of the process uses an etching gas of SiF.sub.4 and one of the high-order hydrofluoroalkanes mentioned by Arleo et al. Marks et al. favor operating at a lower pressure of between 1 and 30 milliTorr, although pressures up to 200 milliTorr are included for some applications. Marks et al. in U.S. Pat. No. 5,423,945 disclose a process for selective etching of oxide over nitride using C.sub.2 F.sub.6 at a pressure of 2 to 30 milliTorr, although CF.sub.4 and C.sub.3 F.sub.8 are mentioned as also preferred. This etching was performed in an inductively coupled high-density plasma reactor with a silicon top electrode. No argon is mentioned.
Recently, high-density plasma (HDP) oxide etchers have become available. Although several methods are available for generating a high-density plasma, the commercially most important configuration uses an RF coil to inductively couple energy into the source region to principally generate the plasma while the pedestal supporting the wafer is a cathode electrode to which RF energy is also applied and which thus biases the wafer relative to the plasma. An example of an HDP oxide etch reactor is the Centura HDP Oxide Etcher available from Applied Materials, Inc. of Santa Clara, Calif. and described by Rice et al. in U.S. Pat. No. 5,477,975. Although HDP etchers offer substantially higher etch rates because of the high plasma density, HDP etchers offer at least two other important, more fundamental advantages.
A first advantage of inductively coupling RF power to generate the plasma is that the bias power applied to the pedestal electrode supporting the wafer can be varied independently of the source power. The bias power determines the sheath voltage adjacent to the wafer and thus determines the energy of ions extracted from the plasma to the wafer. We now know that the typical type of oxide plasma etching, called reactive ion etching, requires both fluorine radicals generated by the plasma and energetic ions impinging the wafer and activating the etching chemistry. The energetic ions may be argon ions used as a carrier gas for the fluorocarbon etching gas. However, if the etch is to stop on silicon, the argon ion energy needs to be reduced to prevent damage to the silicon. A small bias power accomplishes this even though a large source power is generating an intense plasma.
A second advantage of a high-density plasma is that a substantial fraction of the atoms in the plasma are ionized, an ionization density of at least 10.sup.11 /cm.sup.3 being one definition of a high-density plasma. The ionization density tends to be strongly peaked in a source region near the inductive coils and remote from the wafer, and it tends to fall precipitously toward the wafer. Ionized radicals in the plasma are then accelerated across the bias-controlled plasma sheath so that they arrive at the wafer with a forward directed velocity distribution. This anisotropy in the etchant flux promotes anisotropic etching and prevents microloading effects at the bottom of high-aspect ratio holes. However, the directional advantage can be obtained only if the plasma is formed in a low pressure gas. If the source region is separated from the wafer by a distance significantly longer than a mean free path of the ionized radicals, which varies inversely with pressure, then the radicals are likely to collide at least once on their way to the wafer, both randomizing the flux and reducing the likelihood of the radical remaining ionized.
For silicon selectivity, Rice et al. rely upon an etching gas composition of C.sub.2 F.sub.6. Later developments with the same chamber have utilized C.sub.3 F.sub.8 and C.sub.4 F.sub.8, which have the higher C/F ratios desired by Yanagida. Rice et al. also rely upon a hot silicon surface for scavenging fluorine from the plasma. The reduction of fluorine results in high selectivity to silicon. The temperature of the silicon-based scavenger needs to be elevated to above about 200.degree. C. to activate the scavenging, and the temperature of other portions of the chamber need to be controlled relative to the scavenger temperature. Marks et al. describe similar silicon-based scavenging to achieve selectivity to nitride in the aforementioned U.S. Patent application.
Another inductively coupled HDP oxide etch chamber is the IPS Oxide Etcher, also available from Applied Materials and described by Collins et al. in U.S. patent application, Ser. No. 08/733,544, filed Oct. 21, 1996. As shown in FIG. 2, a wafer 30 to be processed is supported on a cathode pedestal 32 supplied with RF power from a first RF power supply 34. A silicon ring 36 surrounds the pedestal 32 and is controllably heated by an array of heater lamps 38. A grounded silicon wall 40 surrounds the plasma processing area. A silicon roof 42 overlies plasma processing area, and lamps 44 and water cooling channels 46 control its temperature. The temperature-controlled silicon ring 36 and silicon roof 42 may be used to scavenge fluorine from the fluorocarbon plasma. Processing gas is supplied from one or more bottom gas feeds 44 through a bank of mass flow controllers 46 under the control of a system controller 48. The process recipe is stored in the system controller 48 in magnetic or semiconductor memory. An unillustrated vacuum pumping system connected to a pumping channel 52 around the lower portion of the chamber maintains the chamber at a preselected pressure.
In the used configuration, the silicon roof 42 is grounded, but its semiconductor resistivity and thickness are chosen to pass generally axial RF magnetic fields produced by an inner inductive coil stack 56 and an outer inductive coil stack 58 powered by respective RF power supplies 60, 62.
An example of the need for wide process windows involves the mass flow controllers 46, which typically have a resolution of about 1 sccm (standard cubic centimeter per minute). Some of the prior art recipes use C.sub.4 F.sub.8 in an HDP etch reactor to achieve high selectivity. However, the process window for these processes have been observed to be in the neighborhood of .+-.1 sccm. Obviously, such a process is difficult to control in a commercial environment. In more general terms, the low resolution of the mass flow controllers argues against any process using only a few sccm of any gas.
It is desired to provide a process for oxide etching that has a wide process window. It is also desired that the process provide other favorable characteristics, such as high selectivity to nitride, a high etch rate, no etch stop, and good verticality. It is further desired that the process be usable in a high-density plasma reactor.